http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-104332413-A

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filingDate 2014-05-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_62bdf5a436934978af5c2fe33b18d460
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publicationDate 2015-02-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CN-104332413-A
titleOfInvention 3D assembling method for integrally integrating chips of T/R assembly
abstract The invention provides a 3D assembling method for integrally integrating chips of T/R assembly, and aims to provide a T/R assembly which has advantages of reliable performance, higher density, more functions, high signal transmission speed, better performance and relatively lower cost. The 3D assembling method is realized through a solution which comprises the steps of performing z-direction expansion on a planar circuit with printed circuit patterns to a green ceramic chip laminate of a three-dimensional circuit through interlayer vertical interconnection; vertically packaging an active device in a rectangular chamber (7) of the green ceramic chip laminate (5), placing a power supply modulator on the back surface of the bottom of the green ceramic chip laminate, and inputting an outer signal from a low-frequency interface at the back surface of the green ceramic chip laminate to a pad of the green ceramic chip laminate (5); performing radio frequency connection among chips through a metal wire bonding vertical interconnection structure among the green ceramic chip laminates, accurately aligning and laminating the green ceramic laminates in a Z direction, and then sintering at a temperature of 900 DEG C, thereby preparing a three-dimensional circuit low-temperature co-sintered ceramic LTCC substrate which is used for high-density circuits with no three-dimensional space interference and is internally provided with a passive element and can be equipped with bare chips or package chips on the surface.
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Total number of triples: 65.