| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-26513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-268
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28167
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28008
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-265
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-266
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-495
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42356
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66568
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4983
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-51
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6659 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-51 |
| filingDate |
2012-11-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2017-10-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2017-10-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-103855014-B |
| titleOfInvention |
P-type MOSFET and its manufacture method |
| abstract |
Disclose a kind of p-type MOSFET and its manufacture method.P-type MOSFET manufacture method includes：Source/drain region is formed in the semiconductor substrate；Interfacial oxide layer is formed on a semiconductor substrate；High-K gate dielectric is formed on interfacial oxide layer；The first Metal gate layer is formed on high-K gate dielectric；Dopant is injected by conformal be entrained in the first Metal gate layer；And annealed to change the effective work function of gate stack, wherein gate stack includes the first Metal gate layer, high-K gate dielectric and interfacial oxide layer. |
| priorityDate |
2012-11-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |