http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-103632966-B

Outgoing Links

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66484
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-24
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1033
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
filingDate 2012-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2016-01-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2016-01-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CN-103632966-B
titleOfInvention The formation method of MOS transistor
abstract A formation method for MOS transistor, comprising: provide substrate; Form back grid, backgate dielectric layer, body region, the first functional layer and front gate dielectric layer from the bottom to top successively at substrate surface, described first functional layer is for improving the migration rate of charge carrier in channel region; Etch described front gate dielectric layer and the first functional layer, form the first groove exposing part body region; Along the first groove, ion implantation is carried out to body region, form heavily doped region; In the first groove, fill metal level, form the connector be connected with heavily doped region; Before between heavily doped region, gate dielectric layer surface forms the second functional layer and normal-gate from the bottom to top successively, and described second functional layer is for reducing the leakage current of channel region.The formation method of MOS transistor of the present invention can regulate the threshold voltage of formed MOS transistor, improves compatibility and the matching degree of each MOS transistor in semiconductor device, improves the performance of formed semiconductor device.
priorityDate 2012-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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