| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3a62c92e56568bd104089aac22ca487b |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17728
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17796
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17736
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17756
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17792 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-177 |
| filingDate |
1998-12-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b13d18223181c1b4b05c4925d116197b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ccc3b04e0efbc1616018c5589f86ebbf
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_507bbbedae89a1d95319deb6da00607c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ee892acfd087ad097bb9ae09b8a580b7 |
| publicationDate |
1999-07-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-9933177-A1 |
| titleOfInvention |
Symmetrical, extended and fast direct connections between variable grain blocks in fpga integrated circuits |
| abstract |
A Field Programmable Gate Array (FPGA) device includes a plurality of variable grain blocks (VGBs) and a plurality of interconnect lines for providing program-defined routing of signals between the VGBs. The VGBs include a plurality of L-organized CBBs (configurable logic blocks) having function-producing resources. Each CBB includes 6 term inputs, 2 control inputs and one direct connect output. Each CBB includes two configurable building elements having 3 term inputs and 1 control input, respectively. The plurality of interconnect lines includes a direct connect architecture for providing programmably-selectable, dedicated connections between a center VGB, in particular a CBB, and neighboring VGBs. The direct connect architecture and positioning of inputs and outputs enables 1) enhanced flexibility and efficiency in the configuration placement and routing software 2) efficiently emulates random logic nets and 3) reduces many direct connect line wire lengths. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-2974025-A4
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9817933-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7000212-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-3480956-A3
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-106528920-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-106528920-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-105191140-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-105191140-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10331840-B2 |
| priorityDate |
1997-12-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |