http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-9808254-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3a62c92e56568bd104089aac22ca487b |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S438-981 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0922 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823857 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-316 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 |
| filingDate | 1997-05-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_922e220d8b71b2f35158448031db1e70 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_73ea192e1c746f038f4f2763dab09af2 |
| publicationDate | 1998-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-9808254-A1 |
| titleOfInvention | Integrated circuit with differing gate oxide thickness and process for making same |
| abstract | A semiconductor process for producing two gate oxide thicknesses within an integrated circuit in which a semiconductor substrate having a first region and a second region is provided. The first region and the second region are laterally displaced with respect to one another. A nitrogen species impurity distribution is then introduced into the first region of the semiconductor substrate. Thereafter, a gate dielectric layer is grown on an upper surface of the semiconductor substrate. The gate dielectric has a first thickness over the first region of the semiconductor substrate and a second thickness over the second region of the semiconductor substrate. The first thickness is less than the second thickness. In a CMOS embodiment of the present invention, the first region of the semiconductor substrate comprises p-type silicon while the second substrate region comprises n-type silicon. Preferably, the step of introducing the nitrogen species impurity distribution into the semiconductor substrate is accomplished by thermally oxidizing the first substrate region in a nitrogen bearing ambient. In a presently preferred embodiment, the nitrogen bearing ambient includes N2O, NH3, O2 and HCl in an approximate ratio of 60:30:7:3. In alternative embodiments the nitrogen bearing ambient includes NO, O2 and HCl in an approximate ratio of 90:7:3 or N2O, O2 and HCl in a approximate ratio of 90:7:3. The introduction of the nitrogen species impurity into first substrate region (102) may alternatively be accomplished with rapid thermal anneal processing. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-19839079-C2 |
| priorityDate | 1996-08-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 29.