http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-9803989-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3a62c92e56568bd104089aac22ca487b |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28123 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66583 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
| filingDate | 1997-05-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_73ea192e1c746f038f4f2763dab09af2 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_922e220d8b71b2f35158448031db1e70 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c55d0cc4a91de873825dabea7996ba1a |
| publicationDate | 1998-01-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-9803989-A1 |
| titleOfInvention | Method of reducing mos transistor gate beyond photolithographically patterned dimension |
| abstract | A semiconductor fabrication process for fabricating MOS transistors in which dielectric spacer structures are used prior to gate formation to reduce the gate length below the minimum feature size resolvable by the photolithography equipment. A semiconductor substrate having a channel region laterally disposed between a pair of source/drain regions is provided. A dielectric stack is formed on an upper surface of the semiconductor substrate and patterned to expose on upper surface of a spacer region of the semiconductor substrate. The spacer region includes the channel region and peripheral portions of the pair of source/drain regions proximal to the channel region. The patterning of the dielectric stack results in the formation of a pair of opposing sidewalls in the dielectric stack. Thereafter, a pair of first spacer structures are formed on the pair of opposing sidewalls such that the pair of first spacer structures cover or shadow the peripheral portions of the source/drain regions and such that an upper surface of the channel region is exposed. A gate structure is then formed on the upper surface of the channel region. The gate structure is laterally disposed between the pair of first spacer structures. A first dopant species is then introduced into the source/drain regions of the semiconductor substrate. |
| priorityDate | 1996-07-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 29.