| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3e56b465956d578c92ff77ce2ad22362 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0813
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-018521
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0831
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-4022
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-4077
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-00361
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-173 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-0185
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-003
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-173
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-40 |
| filingDate |
1997-02-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0c8f9033975f79809dc22a7bca4a365a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c5dbc0b74424f9cfba78f8a8a19dcf9e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_22bd7ff68696d99db2e9491cc742c09e |
| publicationDate |
1997-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-9730399-A1 |
| titleOfInvention |
High-availability super server |
| abstract |
The present invention provides a high-availability parallel processing server that is a multi-processor computer with a segmented memory architecture. The processors are grouped into processor clusters, with each cluster consisting of up to four processors in a preferred embodiment. Each cluster of processors has dedicated memory buses for communicating with each of the memory segments. The invention is designed to be able to maintain coherent interaction between all processors and memory segments within a preferred embodiment. A preferred embodiment uses Intel Pentium-Pro processors. The present invention comprises a plurality of processor segments (a cluster of one or more CPU's) memory segments (separate regions of memory), and memory communication buses (pathways to communicate with the memory segment). Each processor segment has a dedicated communication bus for interacting with each memory segment, allowing different processors parallel access to different memory segments while working in parallel. The processors, in preferred embodiment, may further include an internal cache and flags associated with the cache to allow multi-processor cache coherency in external write-back cache. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-0109741-A2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10042804-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-0111481-A2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-0109741-A3
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6760743-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-0111481-A3 |
| priorityDate |
1996-02-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |