| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_61624f79b3adc0fa7338e386a1d4b526
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_7e93894368bdbe0c97fef37e60b98e4d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9090cb16a6f611bf0dde398995f0668b |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-4881
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-8023 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-80
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-48 |
| filingDate |
1996-12-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_efc924402dc81fe445d8a372c01a7994
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_99d5613d3660e464176d615bd3cf9cdd |
| publicationDate |
1997-06-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-9722926-A2 |
| titleOfInvention |
Integrated circuits for multi-tasking support in single or multiple processor networks |
| abstract |
An integrated circuit (7A) for multitasking support for processing unit (1A) holds control variables for each task (or activity) to run on its associated processor (1A) and identifies the next task that should run. The circuit (7A) employs level-driven, clock free ripple logic and is configured as a two-dimensional array of 'tiles', each tile being composed of simple logic gates and performing a dedicated function. The circuit has particular application to asynchronous multiple processor networks. |
| priorityDate |
1995-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |