http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-9712316-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3a62c92e56568bd104089aac22ca487b |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-49957 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-49926 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-49905 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-4991 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-483 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-57 |
| filingDate | 1996-07-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_53d26868f452692f09aa81360973732c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ca56a4ec2138f686b1161cd0a6ab1732 |
| publicationDate | 1997-04-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-9712316-A1 |
| titleOfInvention | Floating point processing unit with forced arithmetic results |
| abstract | Logic for selectively forcing arithmetic results allows a floating point unit to bypass the normal flow through arithmetic units and pipelines depending on the particular floating point operation and operand conditions. Certain forced results (e.g., forced zeros, infinities, and those corresponding to certain invalid operand conditions) may bypass arithmetic units or pipelines and rounding circuitry entirely. On the other hand, other operand dependent results (e.g., the result of X + 0 and results of operations involving an NaN operand or operands) may only partially bypass the normal flow. By providing logic for selectively forcing results, arithmetic pipelines may be freed for subsequent instructions in the instruction stream. Logic for selectively forcing arithmetic results may be particularly attractive in a superscalar processor. In a superscalar processor which includes a floating point unit with forced arithmetic results, microcode to handle special cases, pipeline bypass, and early result generation can be avoided because architectural approaches for handling out-of-order results allow dependencies to be resolved irrespective of result reordering. Therefore, the early and out-of-order generation of forced results may be handled by a reorder buffer. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113591031-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2008078098-A1 |
| priorityDate | 1995-09-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 22.