| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_903ed018d8aca844227c79f7d8e84281 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-4059
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-405 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B29K23-00 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B32B27-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-42
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B32B5-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B29C39-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C08J9-232
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B29C67-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-00 |
| filingDate |
1996-06-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a41cba212258125bf71800d44cac4382 |
| publicationDate |
1996-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-9641267-A1 |
| titleOfInvention |
Delay reduction in transfer of buffered data between two mutually asynchronous buses |
| abstract |
An interface between first and second data buses (110 and 120) includes a first bus state machine (406) which controls data transfers from the first data bus (110) to a data buffer (132). The interface includes a second bus state machine (404) which controls data transfers from the data buffer (132) to the second data bus (120). A respective valid data flag (170) for each storage location is set by the first bus state machine (406) when data are stored in the storage location (132) from the first data bus (110) and is cleared by the second bus state machine (404) when data are transferred from the storage location (132) to the second data bus (120). In order to reduce the time required to output sequential data from multiple data locations in the data buffer (132), each data valid flag (170) is synchronized independently. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7288973-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7793021-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-9919806-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6949958-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-9741514-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6473439-B1 |
| priorityDate |
1995-06-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |