http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-8701479-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e5db580deca7130dbe51805c6c608b35 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-10 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-04 |
| filingDate | 1986-09-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_41211c0285de1e7fe44240df207e85c4 |
| publicationDate | 1987-03-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-8701479-A1 |
| titleOfInvention | System for adjusting clock phase |
| abstract | A logic circuit equipped with a scan in/out means that is provided with n+p specific scan in/out latch circuits. A first delay means which selectively generates input clocks as delay clock signals of a maximum of m = 2n steps according to selection signals of n bits, is connected in cascade with a second delay means which selectively generates input clock signals as delay clock signals of a minimum step of 1/2p times as small as the width of a minimum step of the clock signals by said first delay means, according to selection signals of p bits. By setting selection data to said n+p scan in/out latch circuits, any delay clock signal can be obtained that is delayed by a given 1/2p step relative to the input clock signal. |
| priorityDate | 1985-09-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID3033151 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419499693 |
Total number of triples: 15.