http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2023272880-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ba08257e440b7610a48f587add409946 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-482 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-33 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-05 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 |
| filingDate | 2021-08-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5a17beb131a4bb3f45c8411ce5f7fc03 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d5b2a241d07e4a389a46b67815dfd294 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_127d4fd3bf212363b9a8eb9e493b5ca8 |
| publicationDate | 2023-01-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2023272880-A1 |
| titleOfInvention | Transistor array and manufacturing method therefor, and semiconductor device and manufacturing method therefor |
| abstract | Provided in the present disclosure are a transistor array and a manufacturing method therefor, and a semiconductor device and a manufacturing method therefor. The method for manufacturing a transistor array comprises: providing a wafer; partially etching the wafer on a first surface of the wafer in a first direction to create grid-shaped etched trenches and a transistor column array, the transistor column array comprising a plurality of transistor columns arranged in an array, the transistor columns being located at grid points of the grid-shaped trenches, a first preset thickness of the transistor columns being less than an initial thickness of the wafer, the first direction being a thickness direction of the wafer, and the first surface being perpendicular to the first direction; depositing an insulating material in the grid-shaped etched trenches to create an insulating layer surrounding the transistor columns; etching the insulating layer to expose side walls of the transistor columns; sequentially forming grid oxide layers and grids on the exposed side walls of the transistor columns; forming source electrodes at first ends of the transistor columns; forming drain electrodes at second ends of the transistor columns, the first ends and the second ends being opposite ends of the transistor columns in the first direction; and forming, by the transistor columns between the source electrodes and the drain electrodes, a channel region of a transistor. |
| priorityDate | 2021-07-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 22.