http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2021134423-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c826a0459b2a9baf1b135ff946a0ea80 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66477 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-786 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 |
| filingDate | 2019-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cb9e4c9c26b57196d5a9bb505ed50373 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a8752c7f65709e3def12638f379033df http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ed56805d72683ddf76758f92a8864cb9 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9a7e2f7b961624ca057b1e4b4c803998 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f305b50bd4f926b37322fdaab6a7b914 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7c437ea29d6847cebc41cbdbc7140baa http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_de73b2ca76126fc03475f2a5ba8cc643 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a814161ca943564ece9a29df13781677 |
| publicationDate | 2021-07-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2021134423-A1 |
| titleOfInvention | Method for preparing thin film transistor |
| abstract | A method for preparing a thin film transistor, comprising: forming a patterned active layer (12) on a base substrate, and sequentially forming an entire gate insulating layer and an entire gate layer (13, 14) on the active layer and the base substrate; forming a patterned photoresist layer on the entire gate layer (15); using the photoresist layer as a mask to pattern the entire gate layer and the entire gate insulating layer (16); using the thinned photoresist layer as a mask to pattern a quasi-gate (18); removing the thinned photoresist layer (19); using a PECVD process to form a first insulating layer on the base substrate, the active layer, the gate insulating layer, and the gate, and using the gate insulating layer and the gate as a mask medium and using plasma of a precursor gas in the PECVD process to carry out high conductivity treatment (20) on the active layer; and forming a source and a drain (21). The difficulty of adjusting a threshold voltage of a thin film transistor is reduced, and high-precision preparation of the thin film transistor with an easily adjustable threshold voltage is achieved. |
| priorityDate | 2019-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 60.