| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f52ff1051e70cfb44f47eb80bf2ca79b |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-221
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-56
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B53-30 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11507
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11509
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L49-02 |
| filingDate |
2020-12-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0d365cce3f6007c0390ac480268d5e11
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5292d41fabdb5407708c5cd75f9bceda
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e914bd8a43482d50788d8726fbf4a98f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7881e5b50415f2013ed1f80e271300ed
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_caf7b286a64cc911a1ef3cd46eb1b6e1 |
| publicationDate |
2021-07-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2021133981-A1 |
| titleOfInvention |
Integration method of ferroelectric memory array |
| abstract |
Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die. |
| priorityDate |
2019-12-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |