http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2021088379-A1

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filingDate 2020-06-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5e03c1924fe726c1d71e934b4f0fdfa8
publicationDate 2021-05-14-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber WO-2021088379-A1
titleOfInvention Semiconductor structure, fabrication method therefor, and semiconductor package structure
abstract The present invention relates to a semiconductor structure, comprising: a base substrate, a solder pad, a first protection layer, a connection plug, a rewiring layer, a bump, and a second protection layer. The rewiring layer comprises a first metal wire and a second metal wire. The second metal wire is not used for any electrical connection. Since the first metal wire and the second metal wire are at the same height, a bump on the first metal wire and a bump on the second metal wire are considered as being formed on the same layer, thereby improving coplanarity of the bump on the first metal wire and the bump on the second metal wire. Since the second metal wire is insulated from the solder pad, as a result, a bump formed on the second metal wire is not used for electrical connections, and transfers a stress generated by warpage of the base substrate to the first protection layer. The present application enables bumps on the base substrate to have superior coplanarity, thereby reducing the probability of poor wetting when performing flip chip packaging on a substrate, and improving package reliability.
priorityDate 2019-11-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 49.