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filingDate 2020-08-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5073c36b1fbfc950cb1f6e6e1c00f6c1
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publicationDate 2021-04-08-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber WO-2021066951-A1
titleOfInvention Method of making multiple nano layer transistors to enhance a multiple stack cfet performance
abstract A semiconductor device is provided. The semiconductor device has a first transistor pair formed over a substrate. The first transistor pair includes a n-type transistor and a p-type transistor that are stacked over one another. The n-type transistor has a first channel region that includes one or more first nano-channels with a first stress. The one or more first nano-channels extend laterally along the substrate, are stacked over the substrate and spaced apart from one another. The p-type transistor has a second channel region that includes one or more second nano-channels with a second stress. The one or more second nano-channels extend laterally along the substrate, are stacked over the substrate and spaced apart from one another. Each of the one or more first nano-channels in thefirst channel region and each of the one or more second nano-channels in the second channel region are surrounded by a gate structure respectively.
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priorityDate 2019-10-03-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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