| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a8e9124416a628c95949615a6600e98f |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02255
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-826
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78642
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8836 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02236
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-826
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02164
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-021
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-80
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42376
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28035
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66568
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-26513 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 |
| filingDate |
2019-03-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b4a7bf3a65bf39c81291c6674b30e0ee
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_52e73cc412b6917db6d88fe48b27419d |
| publicationDate |
2020-09-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2020181410-A1 |
| titleOfInvention |
1t1r resistive random access memory and manufacturing method therefor, transistor and device |
| abstract |
The present application provides a 1T1R resistive random access memory and a manufacturing method therefor, and a device. The 1T1R resistive random access memory comprises: a storage unit array constituted by a plurality of 1T1R resistive storage units, each 1T1R resistive storage unit comprising a transistor and a resistance switching device (30); the transistor comprising a channel layer (201), a gate layer (204) insulated from the channel layer (201), and a drain layer (203) and a source layer (202) provided on the channel layer (201), the drain layer (203) and the source layer (202) being longitudinally distributed on the channel layer (201); the resistance switching device (30) being provided close to the drain layer (203). The present application reduces the area of a transistor, so that the storage density of resistive random access memories is significantly increased, thereby solving the problem that the storage density of existing 1T1R resistive random access memories is limited due to the fact that the area of a transistor cannot be reduced. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2023029563-A1 |
| priorityDate |
2019-03-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |