http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2020154983-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0cff927aae3d9124547c4594ced4af2e |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-34 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09F9-30 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09F9-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-34 |
| filingDate | 2019-01-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f5625688e58c5aeefe5207efddd9e28a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dcc0d64b25969c04561cd5bf960421dd |
| publicationDate | 2020-08-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2020154983-A1 |
| titleOfInvention | Thin film transistor and fabrication method therefor, display panel and display device |
| abstract | Disclosed in embodiments of the present application are a thin film transistor and a fabrication method therefor, a display panel and a display device; the thin film transistor (10) comprises a first gate layer (11), a first insulating layer (12), an active layer (13), a second insulating layer (14), a second gate layer (15), a third insulating layer (16) and a drain source layer (17) that are successively stacked; the plane on which the active layer (13) is located is used as a projection plane; and the orthographic projection of the first gate layer (11) on the projection plane and the orthographic projection of the second gate layer (15) on the projection plane at least partially overlap. Since between the first gate layer (11) and the active layer (13) as well as between the second gate layer (15) and the active layer (13) both do not constitute conditions for generating parasitic capacitance, the present invention may reduce parasitic capacitance. |
| priorityDate | 2019-01-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 46.