http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2020114660-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_504230c35fe1cc2b0173c8f688be1281 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-1033 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-10272 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01042 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-72 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01013 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-72 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-62 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-07 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-62 |
| filingDate | 2019-10-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a1fcc72229abe52585cdbee118a1ea73 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_659b3e5ced94c124a2f64bdbf2d267b7 |
| publicationDate | 2020-06-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2020114660-A1 |
| titleOfInvention | Hybrid short circuit failure mode preform for power semiconductor devices |
| abstract | A power semiconductor module comprises a base plate (1); a semiconductor chip (2) disposed on and in contact with a top surface of the base plate (1), a preform (3) disposed on and in contact with a top surface of the semiconductor chip (2); and a pressing element (4) in contact with and applying a pressure onto a top surface of the preform (3). The preform (3) comprises a first electrically conductive layer (6) and a second electrically conductive layer (5). The first electrically conductive layer (6) has at least one protrusion (7) protruding towards the top surface of the semiconductor chip (2) and defining a recess (9) in the first electrically conductive layer (6) of the preform (3), wherein the recess (9) may annularly surround the protrusion (7). The at least one protrusion (7) is made from the same material as the first electrically conducting layer (6) and integrally formed with it or the first electrically conducting layer (6) and the at least one protrusion (7) are made from different materials. At least a portion of the second electrically conductive layer (5) is positioned in the recess (9) and on the top surface of the semiconductor chip (2). The material of the at least one protrusion (7) has a higher melting point than the material of the second electrically conductive layer (5). The power semiconductor module is configured so that in an event of semiconductor chip failure with heat dissipation, the protrusion (7) of the first electrically conductive layer (6) penetrates through residual material (8) of the semiconductor chip (2) upon pressure applied by the pressing element (4) towards the base plate (1) so as to establish a contact between the protrusion (7) of the first electrically conductive layer (6) and the base plate (1) and form a short circuit bridging the defective semiconductor chip (2) in a short circuit failure mode. The bottom surface of the preform (3) may be formed by a bottom surface of the second electrically conductive layer (5) alone or by a bottom surface of the second electrically conductive layer (5) and a bottom surface of the protrusion (7). |
| priorityDate | 2018-12-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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