http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2020105265-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0ddb9f3656270bc5410be3679322fead |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02P70-50 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02E10-50 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L31-0747 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L31-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-308 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L31-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L31-0747 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-308 |
| filingDate | 2019-09-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5da8c6344f012c279a6d8d5c361b0b92 |
| publicationDate | 2020-05-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2020105265-A1 |
| titleOfInvention | Method for manufacturing solar cell |
| abstract | The present invention provides a solar cell manufacturing method with which solar cells having high performance can be manufactured more efficiently compared to conventional art. The invention comprises: a first semiconductor layer formation step for forming a first semiconductor layer on a first principal surface side of a semiconductor substrate; a lift-off layer lamination step for laminating a lift-off layer on the first semiconductor layer; a patterning step for selectively removing each of the first semiconductor layer and the lift-off layer; a second semiconductor layer formation step for forming a second semiconductor layer on the first principal surface side in a manner extending from a section where the first semiconductor layer and the lift-off layer have been removed and spanning a section where the first semiconductor layer and the lift-off layer are laminated; and a lift-off step for removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer. In the patterning step, the first semiconductor layer and the lift-off layer are removed by using a plurality of types of etching solutions so that the etching area of the first semiconductor layer becomes equal to or less than the etching area of the lift-off layer. The lift-off layer includes a metal as a main component. |
| priorityDate | 2018-11-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 43.