http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2020090601-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6a162b65402a9a79580e3ae31dcbf3fa |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73204 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16225 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32225 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15311 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-32 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-46 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-32 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-46 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60 |
| filingDate | 2019-10-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b81d72cbc7d34b515ed67627137bae58 |
| publicationDate | 2020-05-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2020090601-A1 |
| titleOfInvention | Semiconductor packaging wiring substrate and method of manufacturing semiconductor packaging wiring substrate |
| abstract | Provided is a wiring substrate with which it is possible to suppress a decrease in the yield of an FC-BGA wiring board with an interposer and to mount a semiconductor chip well, and which has high reliability. A semiconductor packaging wiring substrate has an interposer 3 bonded to an FC-BGA wiring board 1. The interposer has a thickness of from 10 μm to 1000 μm, and a semiconductor chip-connecting pad 14 connected to the semiconductor chip 4 is provided on a surface of the interposer on the side opposite to the FC-BGA wiring board. The semiconductor chip-connecting pad is a stacked body of metal material with an Au layer on the uppermost surface thereof, wherein the surface of the Au layer is provided in a recess lower than the surface of a surrounding insulating resin 15 by a range of from 0.3 to 5.0 μm. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2022080152-A1 |
| priorityDate | 2018-10-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 34.