http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2020073471-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0cff927aae3d9124547c4594ced4af2e |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2300-0814 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2300-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2300-0408 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2300-0426 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0267 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0202 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0286 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2300-0857 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0291 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3266 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-20 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-36 |
| filingDate | 2018-12-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4a2dc3e3f8ee1331649a3f242e324f51 |
| publicationDate | 2020-04-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2020073471-A1 |
| titleOfInvention | Goa circuit, display device and display control method |
| abstract | A GOA circuit, a display device and a display control method. The GOA circuit comprises a plurality of mutually independent GOA units (10), and each GOA unit (10) comprises an enable module (11) and a drive module (12) disposed corresponding to the enable module (11). The enable module (11) comprises an input end of a row address signal for receiving the row address signal and an enable signal output end for outputting an enable signal according to the row address signal; and the drive module (12) comprises an enable signal input end for receiving the enable signal output from the enable signal output end, and a drive signal output end for outputting a drive signal according to the enable signal, wherein the drive signal output end is connected to gate lines of a row disposed corresponding to the drive module (12), so as to send the drive signal to the gate lines of the corresponding row and gate the corresponding row. The GOA circuit supports random addressing and has high product yield and low power consumption, the reset operation does not rely on external clock signals, and the quality of an output waveform is high. |
| priorityDate | 2018-10-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 45.