| abstract |
Provided is a layout structure of a high-voltage capacitive element in which VNW FET is used. Parts (g11, g21) that each constitute a transistor are arranged in an X-direction. From the part (g11), a gate wiring (21) extends in a direction opposite to the part (g21), and a top wiring (31) and a bottom wiring (11) extend toward the part (g21). From the part (g21), a gate wiring (22) extends toward the part (g11), and a top wiring (32) and a bottom wiring (12) extend in a direction opposite to the part (g11). The top wiring (31), the bottom wiring (11), and the gate wiring (22) are connected. |