| abstract |
This semiconductor device has a structure formed by alternately disposing, in parallel, N layers of gate electrode layers G and (N-1) layers of channel forming region layers CH (where N≥3) on an insulating material layer 61 of a substrate where the insulating material layer 61 is formed on the surface of a conductive substrate 60. The structure, the channel forming region layers CH, and the gate electrode layers G each have a bottom surface, a top surface, and four side surfaces. A second surface 32 and a fourth surface 34 of the n-th channel forming region layer respectively contact the fourth surface 24 of the n-th gate electrode layer and the second surface 22 of the (n+1)-th gate electrode layer. One of an odd-numbered gate electrode layer and an even-numbered gate electrode layer is connected to a first contact part, and the other is connected to a second contact part. |