http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2019148571-A1

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Predicate Object
assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d408da059f09751318c9eb2410109ddb
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filingDate 2018-03-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_11e3bfad88859d56f306b9bd2007639f
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publicationDate 2019-08-08-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber WO-2019148571-A1
titleOfInvention Comparator circuit for high-speed pipelined adc
abstract A comparator circuit for a high-speed pipelined ADC, capable of improving transmission rates of a sampling phase and a settling phase, and comprising a switched capacitor circuit 110, a pre-amplifier circuit 120, and a latch circuit 130. The pre-amplifier circuit 120 can comprise a pre-amplifier A1, a resistance modulating device R1, a first switch S1, and a second switch S2. The latch circuit 130 comprises a differential static latch A2, a first capacitor C1, a second capacitor C2, and a third switch S3. A first output terminal Vp of the switched capacitor circuit 110 is connected to a non-inverting input terminal of the pre-amplifier A1, and a second output terminal Vn is connected to an inverting input terminal of the pre-amplifier A1. An inverting output terminal of the pre-amplifier A1 is connected to a first terminal of the first switch S1, and a second terminal of the first switch S1 acts as a first output terminal VLN of the pre-amplifier circuit 120 and connects to a positive input terminal of the differential static latch A2. A non-inverting output terminal of the pre-amplifier A1 is connected to a first terminal of the second switch S2, and a second terminal of the second switch S2 acts as a second output terminal VLP of the pre-amplifier circuit and connects to a negative input terminal of the differential static latch A2. A positive output terminal of the differential static latch A2 is connected to the positive input terminal thereof via a first capacitor C1, a negative output terminal of the differential static latch A2 is connected to the negative input terminal thereof via a second capacitor C2, and the third switch S3 is disposed between the positive output terminal and the negative output terminal of the differential static latch A2.
priorityDate 2018-02-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 21.