| abstract |
Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a gate electrode above a substrate and a channel layer above the gate electrode. A source electrode may be above the channel layer and adjacent to a source area of the channel layer, and a drain electrode may be above the channel layer and adjacent to a drain area of the channel layer. A sealant layer may be next to the source electrode and next to the channel layer; or next to the drain electrode and next to the channel layer. The sealant layer may act as a passivation layer and as at least one of a hermetic sealant layer against oxygen or hydrogen exchange, an etching stop layer, or a hard mask layer. Other embodiments may be described and/or claimed. |