http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2019074796-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-361 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1006 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-10 |
| filingDate | 2018-10-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2b2f493bb6c82882ee590821897badcc |
| publicationDate | 2019-04-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2019074796-A1 |
| titleOfInvention | APPARATUSES AND METHODS FOR PARALLEL I / O OPERATIONS IN A MEMORY |
| abstract | Devices and methods for multi-level communication architectures are disclosed. An exemplary apparatus may include an input / output (I / O) circuit comprising a driver configured to convert a first bit stream directed to a first memory device and a second directed bit stream. to a second memory device into a single multi-level signal. The driver circuit is further configured to drive the multi-level signal on a signal line coupled to the first memory device and the second memory device using a driver configured to drive more than two voltages. |
| priorityDate | 2017-10-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 17.