| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bbc4a196ac5f96d87d8fd16b5577edab
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0020af9d1f0c813f1f85fce3b01fb7ca |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-92125
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-131
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73204
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-92
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-73
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16227
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48227
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-16 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-4857
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49838
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49894 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-485
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-07 |
| filingDate |
2017-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e1e2bce30f5164629ca7165e3fedaf34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_95fcbb116924db96f6d16363329593cc |
| publicationDate |
2019-01-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2019005116-A1 |
| titleOfInvention |
SEMICONDUCTOR HOUSING AND METHOD OF MANUFACTURING |
| abstract |
The present invention relates to a substrate for an integrated circuit. The substrate comprises a dielectric layer. The substrate further comprises a plurality of conductive elements at least partially integrated within the dielectric layer and having a substantially smooth outer surface. The substrate further comprises an intermediate layer disposed between the individual conductive elements and the dielectric layer. The intermediate layer has a first surface including a plurality of protrusions interlocked with the dielectric layer and a second surface bonded to the outer surface of the individual conductive elements. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11257748-B2 |
| priorityDate |
2017-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |