| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c5520dd38cc403678d9f91e0b0ee95fb |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1251
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K59-1213
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1222
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1259
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78648
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78645 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 |
| filingDate |
2018-05-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_09ef70fa2d20d37184cb744c1bcd91ee |
| publicationDate |
2018-12-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2018221294-A1 |
| titleOfInvention |
Active matrix substrate and method of manufacturing same |
| abstract |
An active matrix substrate according to an embodiment of the present invention is provided with: a substrate; a plurality of first TFTs supported by the substrate and provided in a non-display region; and a peripheral circuit including the plurality of first TFTs. Each of the first TFTs includes: a first gate electrode provided on the substrate; a first gate insulating layer covering the first gate electrode; a first oxide semiconductor layer facing the first gate electrode with the first gate insulating layer therebetween; and a first source electrode and a first drain electrode which are respectively connected to a source contact region and a drain contact region of the first oxide semiconductor layer. Each of the first TFTs has a bottom contact structure. The thickness of a first region of the first gate insulating layer is smaller than the thickness of a second region of the first gate insulating layer, wherein said first region overlaps a channel region, and said second region overlaps the source contact region and the drain contact region. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11695016-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2020172971-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2022005839-A1 |
| priorityDate |
2017-05-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |