Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e6d67894a893256e5b4d85401e466143 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06506 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-13091 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06582 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48137 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76895 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0655 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76829 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-4824 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-535 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41758 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-50 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-48 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-482 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
filingDate |
2017-03-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_66ededae8e15ffccee601a53ac543e35 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fa2bc8b184a632f99b34c34e929f9008 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a1ce18c4444972760f077b419294e87e |
publicationDate |
2017-10-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
WO-2017172897-A1 |
titleOfInvention |
Contact expose etch stop |
abstract |
The present disclosure relates to semiconductor devices and the teachings thereof may be embodied in metal oxide semiconductor field effect transistors (MOSFET). Some embodiments may include a power MOSFET with transistor cells, each cell comprising a source and a drain region; a first dielectric layer disposed atop the transistor cells; a silicon rich oxide layer on the first dielectric layer; grooves through the multi-layered dielectric, each groove above a respective source or drain region and filled with a conductive material; a second dielectric layer atop the multi-layered dielectric; openings in the second dielectric layer, each opening exposing a contact area of one of the plurality of grooves; and a metal layer disposed atop the second dielectric layer and filling the openings. The metal layer may form at least one drain metal wire and at least one source metal wire. The at least one drain metal wire may connect two drain regions through respective grooves. The at least one source metal wire may connect two source regions through respective grooves. Each groove has a length extending from the at least one drain metal wire to the at least one source metal wire in an adjacent pair. |
priorityDate |
2016-03-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |