| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a62555ff12316a9a118542896b4c0af7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-134372 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1214
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-124
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1251
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-1368
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1259
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-127
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1288 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-1368
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-1343
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-77 |
| filingDate |
2015-10-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bc943d427825919c52017b696cecb094
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_08f67c0a12b16ea75022c446764a7327 |
| publicationDate |
2017-05-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2017070890-A1 |
| titleOfInvention |
Array substrate and fabricating method thereof, display panel, and display apparatus |
| abstract |
An array substrate and fabricating method thereof, a display panel, and a display apparatus are provided. A first active layer (120a) and common electrodes (125) are formed on the substrate (110). A first gate insulating layer (130a) is formed on the first active layer (120a). A gate electrode (140a) is formed on the first gate insulating layer (130a). A second gate insulating layer (160) is formed on the common electrodes (125) and the gate electrode (140a). Via-holes (165) are formed in the second gate insulating layer (160) to expose surface portions of the common electrodes (125). Source/drain electrodes (170s/d) are formed and electrically connected to the common electrodes (125) through the via-holes (165). A second active layer (180a) and pixel electrodes (185) are formed on the second gate insulating layer (160). |
| priorityDate |
2015-10-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |