http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2017052837-A1

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publicationDate 2017-03-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber WO-2017052837-A1
titleOfInvention Double affine mapped s-box hardware accelerator
abstract A processing system includes a memory and a cryptographic accelerator module operatively coupled to the memory, the cryptographic accelerator module employed to implement a byte substitute operation by performing: a first mapped affine transformation of an input bit sequence to produce a first intermediate bit sequence, an inverse transformation of the first intermediate bit sequence to produce a second intermediate bit sequence, and a second mapped affine transformation of the second intermediate bit sequence to produce an output bit sequence.
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Total number of triples: 24.