| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1f1132cfcd850b4afa5da3f9e093c614
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-161
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66492
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66636
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823412
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8232
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06 |
| filingDate |
2016-09-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fc537f679c4a93c61abb58f9f1f7c400
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b20eca7d692b0e04bc2550a0f1f01e75 |
| publicationDate |
2017-03-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2017041098-A1 |
| titleOfInvention |
Embedded sige process for multi-threshold pmos transistors |
| abstract |
In described examples of an integrated circuit and method having a first PMOS transistor (205) with extension (210) and pocket implants (212) and with SiGe source and drains (230) and having a second PMOS transistor (215) without extension and without pocket implants and with SiGe source and drains (230), the distance (C2Gd) from the SiGe source and drains (230) to the gate of the first PMOS transistor (205) is greater than the distance (C2Gu) from the SiGe source and drains (230) to the gate of the second PMOS transistor (215), and the turn on voltage of the first PMOS transistor (205) is at least 50 mV higher than the turn on voltage of the second PMOS transistor (215). |
| priorityDate |
2015-09-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |