| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b6caea61bfde8a45e01a8deabff80d97 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-27 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 |
| filingDate |
2016-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9164521348066100b8fc674b6ea86fc8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c02572981ba2bfb0272532e9bee3d429
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b5c649452c600ca137fd18123021b3a5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4d9791ddfed64333f669fc6b9c40f039
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_24145908eb83c165b258c3a81654deaf
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b2299a025a2aed6b0c65d5bff46b62bc |
| publicationDate |
2016-10-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2016167984-A1 |
| titleOfInvention |
A metal-semiconductor alloy region for enhancing on current in a three-dimensional memory structure |
| abstract |
Resistance of a semiconductor channel in three-dimensional memory stack structures can be reduced by forming a metal-semiconductor alloy region between a vertical semiconductor channel and a horizontal semiconductor channel located within a substrate. The metal-semiconductor alloy region can be formed by recessing a portion of the semiconductor material layer in the semiconductor substrate underneath a memory opening after formation of a memory film, selectively depositing a metallic material in the recess region, depositing a vertical semiconductor channel, and reacting the deposited metallic material with an adjacent portion of the semiconductor material layer and the vertical semiconductor channel. A sacrificial dielectric material layer can be formed on the memory film prior to the selective deposition of the metallic material. The vertical semiconductor channel can be formed in a single deposition process, thereby eliminating any interface therein and minimizing the resistance of the vertical semiconductor channel. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112652629-A |
| priorityDate |
2015-04-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |