http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2016032665-A1

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filingDate 2015-07-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c0e4d78efd74445f39888a3dd178ed21
publicationDate 2016-03-03-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber WO-2016032665-A1
titleOfInvention Foreground and background bandwidth calibration techniques for phase-locked loops
abstract Certain aspects of the present disclosure support a method and apparatus for foreground and background bandwidth calibration in a frequency-do-digital converter based phase-locked loop (FDC-PLL) device.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11777510-B2
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Total number of triples: 24.