| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_82a9e22a923eca64a02a97f0dfb493ed |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76895
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823412
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2027-11866
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2027-11861
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2027-11831 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76895
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-118
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 |
| filingDate |
2015-02-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7ac3be19473dbdf54f13d43fc32803da
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dad8d5052a3b9710ac4465814ab55781
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5ad5dd19af87f3274acedf297ad7832d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_51bf4aeb64ed1bd65a8c309ef9b05fa0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ff38197796d9892f4209d2d14458f14f |
| publicationDate |
2015-09-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2015134202-A1 |
| titleOfInvention |
High performance standard cell |
| abstract |
A transistor cell is provided that includes a continuous oxide definition (OD) region defined in a substrate; a gate (450) for a transistor between a first dummy gate (425) and a second dummy gate (430), wherein a source for the transistor is defined in a first portion of the OD region between the gate and the first dummy gate, and wherein a drain for the transistor is defined in a second portion of the OD region between the gate and a first side of the second dummy gate; a first gate-directed local interconnect (470) and a first diffusion- directed local interconnect (440) couple a third portion of the OD region adjacent a second opposing side of the second dummy gate and the second dummy gate to a source voltage. |
| priorityDate |
2014-03-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |