http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2015090008-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a62555ff12316a9a118542896b4c0af7 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K59-124 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1248 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-77 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 |
| filingDate | 2014-05-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2932e798d694bb9854b72bdebd42dd63 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_02ba4ab1f51c9dfc129e3f889317687e |
| publicationDate | 2015-06-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2015090008-A1 |
| titleOfInvention | Array substrate and manufacturing method therefor, and display device |
| abstract | Provided are an array substrate and a manufacturing method therefor, and a display device. The manufacturing method for an array substrate comprises: providing an underlayment substrate (4); forming a film layer (3) of a gate electrode, a gate insulating layer, an active layer, and a source/drain electrode layer on the underlayment substrate (4); forming a passivation layer (2) on the film layer (3); before a conductive pattern is manufactured, patterning the passivation layer (2) using a mask plate for manufacturing a pixel electrode, so that a slope exists at the pattern edge of the passivation layer corresponding to the pixel electrode; and depositing a transparent conducting layer (1), and patterning the transparent conducting layer (1) using the mask plate for manufacturing the pixel electrode, so as to form the conductive pattern. The thickness of the transparent conducting layer (1) at the slope is thinner than that of the transparent conducting layer (1) at other flat places, so that it can be guaranteed that there is no residual on the perimeter of the etched conductive pattern. |
| priorityDate | 2013-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 23.