http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2015016994-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5d89a1fdfad4ceb45818cee0bfda31a6 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-602 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-72 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-76 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F21-76 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F21-72 |
| filingDate | 2014-05-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f139a17fef7685402bbb3c296a0937a1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1507d143ebc252594be8bf54a2e45a42 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8d2b56ec9d534afbaaab6f89e6183fd3 |
| publicationDate | 2015-02-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2015016994-A1 |
| titleOfInvention | System for processing an encrypted instruction stream in hardware |
| abstract | A system and method of processing an encrypted instruction stream in hardware is disclosed. Main memory stores the encrypted instruction stream and unencrypted data. A central processing unit (CPU) is operatively coupled to the main memory. A decryptor is operatively coupled to the main memory and located within the CPU. The decryptor decrypts the encrypted instruction stream upon receipt of an instruction fetch signal from a CPU core. Unencrypted data is passed through to the CPU core without decryption upon receipt of a data fetch signal. |
| priorityDate | 2013-07-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 26.