| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1f1132cfcd850b4afa5da3f9e093c614
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0629
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-12 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-26513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823412
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66477
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823425 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8232
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792 |
| filingDate |
2014-07-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_149b8e9f86e347a3f35b7ef8c3a6522a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3bb93abcd736b7d92fe8453aabfc5443
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d41e4aad85eaabbdbc5c23416fe94464 |
| publicationDate |
2015-01-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2015009791-A1 |
| titleOfInvention |
Integrated circuit and method of forming the integrated circuit |
| abstract |
In described examples, an integrated circuit (100) includes a substrate (110) having a first conductivity type, a logic region, and a memory region. A trench isolation structure (112) touches the substrate (110). A logic transistor (114) has: a logic gate dielectric (126) that touches and lies over the logic region of the substrate (110); and a logic gate (130) that touches and lies over the logic gate dielectric (126). A memory transistor (116) has: a memory gate dielectric (146) that touches and lies over the memory region of the substrate (110); and a memory gate (150) that touches and lies over the memory gate dielectric (146). A resistor (118) touches and lies over the trench isolation structure (112). The resistor (118) has a dopant concentration that is substantially equal to a dopant concentration of the memory gate (150) and substantially less than a dopant concentration of the logic gate (130). |
| priorityDate |
2013-07-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |