| abstract |
A semiconductor power chip comprises a semiconductor die (102, 140, 172, 173, 210, 220, 230, 240, 240') having a power device, for example a power field effect transistor, fabricated on a substrate (210) thereof, wherein the power device has at least one first contact element (e.g. a gate contact element) (110), a plurality of second contact elements (source contact elements) (120) and a plurality of third contact elements (drain contact elements) (130) arranged on top of the semiconductor die (102, 140, 172, 173, 210, 220, 230, 240, 240'); and an insulation layer (150) disposed on top of the semiconductor die (102, 140, 172, 173, 210, 220, 230, 240, 240') and patterned to provide openings (104, 106, 108, 154, 154', 156, 156', 158, 158') to access the plurality of second (120) and third (130) contact elements and the at least one first contact element (110). The gate (104, 154, 154') and drain (108, 158, 158') openings in the insulation layer (150) are arranged on one side of the top surface of the die (102, 140, 172, 173, 210, 220, 230, 240, 240') and the source (106, 156, 156') openings are arranged on the opposite side of the top surface of the die (102, 140, 172, 173, 210, 220, 230, 240, 240'). The openings in the insulation layer (150) are circular (104, 106, 108) or preferably elliptic (154, 154', 156, 156', 158, 158'). Solder or conductive epoxy bumps (160) are placed in the openings (104, 106, 108, 154, 154', 156, 156', 158, 158') for bonding the first (110), second (120) and third (130) contacts to lead frame fingers (204, 204', 206, 206', 208). The lead frame is optionally substantially larger than the die (220, 230) of the semiconductor power chip. The lead frame may connect together a source of a first semiconductor chip with a drain of a second semiconductor chip or sources of a first and a second semiconductor chip. A further chip (620) may be wire-bonded to the lead frame. |