http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2014044752-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9884b2360f2413d7edea0d5af39f775a |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-44 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-156 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-0016 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-56 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-60 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-405 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-15 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L33-44 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L33-40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L33-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L33-08 |
| filingDate | 2013-09-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3184840a1b400bf7a4140d9ffa3fd103 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a47d8efb378eb16888543409b32e54ea |
| publicationDate | 2014-03-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2014044752-A1 |
| titleOfInvention | Optoelectronic semiconductor chip having a plurality of active regions arranged alongside one another |
| abstract | An optoelectronic semiconductor chip (1) is specified, comprising: - a semiconductor layer sequence (2) having an active zone (4) suitable for emitting radiation, - a carrier substrate (10), and - a mirror layer (6) arranged between the semiconductor layer sequence (2) and the carrier substrate (10), wherein - the semiconductor layer sequence (2) is subdivided into a plurality of active regions (11, 12) which are arranged alongside one another and which are respectively separated from one another in the semiconductor layer sequence (2) by a trench (13), wherein each trench (13) severs both the semiconductor layer sequence (2) and the mirror layer (6), - the mirror layer (6) has side surfaces (16) facing a trench (13) and side surfaces (17) facing an outer side (15) of the semiconductor chip (1) - the side surfaces (17) of the mirror layer (17) that face an outer side (15) of the semiconductor chip (1) have a metal encapsulation layer (7) and - at least one portion of the side surfaces (16) of the mirror layer (6) that face a trench (13) has a dielectric encapsulation layer (9). |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2018525821-A |
| priorityDate | 2012-09-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 37.