| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1476752f2420c8f8eb53464cf7fc922b |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-2003
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3171
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-291
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-561
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-408
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66477
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-022
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02178
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02274
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0228 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-316
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate |
2013-06-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6845ca40e60e16bb44080ec7afc05842
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_68518c41f38fef78c2ae587dd8328fa4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1ac0794e732c516b02208f1adcd125a3 |
| publicationDate |
2014-01-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2014010405-A1 |
| titleOfInvention |
Transistor and transistor manufacturing method |
| abstract |
The purpose of the present invention is to provide a transistor, which has a high breakdown voltage of a gate insulating film, while suppressing deterioration of a current flowing between drain/source electrodes.nA transistor (100) is characterized in being provided with: a semiconductor layer (2); a gate insulating film (7) formed on the semiconductor layer (2); a gate electrode (8) formed on the gate insulating film (7); and a source electrode (5) and a drain electrode (6), which are formed on the semiconductor layer (2) with the gate electrode (8) sandwiched between the electrodes. The transistor is also characterized in that the concentration of an impurity contained in the gate insulating film (7) is reduced toward the gate insulating film (7) surface on the gate electrode (8) side from the gate insulating film (7) surface on the semiconductor layer (2) side. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-WO2015166572-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2016018888-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2016171117-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-105304712-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2019071497-A |
| priorityDate |
2012-07-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |