http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2013180757-A1

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filingDate 2013-05-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e84c2cf68162f7d5fcb06b0dca187f51
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publicationDate 2013-12-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber WO-2013180757-A1
titleOfInvention Method of fabricating a gate-all-around word line for a vertical channel dram
abstract A method of fabricating a self-aligned buried wordline in a structure which contains a self-aligned buried bit line, where the overall structure which makes up a portion of a vertical channel DRAM. The materials and processes used enable self-alignment of elements of the buried wordline during the fabrication process. In addition, the materials and processes used enable for formation of individual DRAM cells which have a buried bit line width which is 16 nm or less and a perpendicular buried wordline width which is 24 nm or less.
priorityDate 2012-05-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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