| abstract |
There is provided a semiconductor stud bump wafer level package (110, 201, 301) and a manufacturing method thereof, comprising a semiconductor die (112, 212a, 212b, 312a, 312b) having a plurality of bond pads (130) on a top surface thereof, a plurality of metallic (e.g. copper) stud bumps (120, 220, 320) mechanically and electrically coupled to said plurality of bond pads (130), a plurality of solder balls (160, 260, 360) mechanically and electrically coupled to said plurality of metallic stud bumps (120, 220, 320) and a mould compound (140, 240, 340) encapsulating the plurality of metallic stud bumps (120, 220, 320) while exposing a top surface of each of the plurality of metallic stud bumps (120, 220, 320). In one embodiment, singulation of the wafer (101) is performed after connecting the solder balls (160) to the stud bumps (120) and subsequent testing of die proper functionality and die marking. In another embodiment, singulation of the wafer is performed before forming the mould compound (240), wherein singulated dies (212a, 212b) are mounted on a substrate (215) and subsequently encapsulated. In still another embodiment, singulated dies (312a, 312b) are mounted on a substrate (315) and bond pads (330a, 330b) at die perimeter are wire-bonded to the substrate (315), advantageously during the same manufacturing step as when the stud bumps (360) are formed, after which the moulded compound (340) is formed. Advantageously, the metallic stud bumps (120, 220, 320) may be provided using standard wirebonding equipment by directly bonding to a die bond pad (130), for example having a single aluminium finish, avoiding the conventional wafer level package requirement for photolithography and deposition steps to provide a multi-layer metallic routing structure to an array of under bump metal (UBM) pads. As a result, reduced cycle times, lower cost, and reduced complexity may be provided. |