http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2013033877-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_2e919f1fc599e411c5ff803899b04d97 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b035cf97de2b599f6e2d934bf404f19e http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_80b461ec995bf5f45d61a4a53a70ec41 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d0a3d10ed9477633fd2c07c6da61dc49 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-124 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-743 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1218 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2011-11-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dda42b9abf248ae81589578542e10882 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1161fcb91042ba4b4ac7afce8d16515c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4237ca39b1f9e5d20a286b93e22326e4 |
| publicationDate | 2013-03-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2013033877-A1 |
| titleOfInvention | Semiconductor structure and manufacturing method thereof |
| abstract | A semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises: a semiconductor base; a first insulating material layer, a first conducting material layer, a second insulating material layer, a second conducting material layer, and an insulating buried layer that are sequentially formed on the semiconductor base; a semiconductor layer combined on the insulating buried layer; transistors formed on the semiconductor layer, a channel region of the transistor being formed in the semiconductor layer and having a back gate formed by the second conducting material layer; a dielectric layer covering the semiconductor layer and the transistors; an isolation structure for at least electrically isolating each transistor from adjacent transistors, the top of the isolation structure being flush with or slightly higher than the upper surface of the semiconductor layer, and the bottom of the isolation structure being located in the second insulating material layer; and a conducting contact running through the dielectric layer and extending downwards into the first conducting material layer. |
| priorityDate | 2011-09-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 30.