| abstract |
A TFT substrate has gate electrodes (1012a, 1012b) formed on a substrate (1011), and an insulating layer (1013) covering the tops thereof. The top of the insulating layer (1013) has source electrodes (1014a, 1014b) and drain electrodes (1014c, 1014d) formed thereon with intervals therebetween one another in the Y-axis direction, and connection wiring (1015) also formed thereon. The connection wiring (1015) is connected to the drain electrode (1014c). The top of the insulating layer (1013) also has partition walls (1016) formed thereon in which openings (1016a-1016c) are formed in a manner such that electrodes (1014a-1014d) and the connection wiring (1015) are exposed. The flank-surface sections of the partition walls (1016) facing the openings (1016b, 1016c) are sloped surfaces. Flank-surface sections (1016e, 1016f) are formed so as to have more gradual slopes than the other flank-surface sections (1016d, 1016g, 1016h-1016k) are. |