| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_43f0c3b5a1bdc7ff5e08b084a7a40054
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_092b0d5cc36970818f05969dc38b9c9d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b809e16fc8e6cf409abc8b3376cda1d2 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1044 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-10 |
| filingDate |
2010-09-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ec67a4bd2c995a4df6a3faceca0049e5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a34212629450d9b81dd48fd7dadb258a |
| publicationDate |
2011-03-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2011034784-A1 |
| titleOfInvention |
Nonvolatile memory controller with scalable pipelined error correction |
| abstract |
A nonvolatile memory system includes a memory controller in communication with multiple memory dies through multiple memory interfaces. Multiple ECC blocks are provided to decode data from the multiple memory interfaces. ECC blocks are provided with a clock signal that may have a frequency that is lower than another clock signal that is provided to a host interface. |
| priorityDate |
2009-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |