| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6fc946377c50d4810b380df6bc77e596
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_7212b08200b390e3dccb58e6f31bcafa
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e7584a4b4b7e7300b30137d6e151fa1b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_2572eea64db35863f24d0a92c50e0699
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_82a9e22a923eca64a02a97f0dfb493ed |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-00011
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-00014
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06517
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06541 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-562
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0657
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-00 |
| filingDate |
2010-06-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_936058b026ad0925290a4f393e2bc0dd
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b05da051f30cf72aa0c4761d9a2eb760
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1f61d832cb9a362bb6640fe865674976
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_62fd51515f7f0d6f0a187c97361d6ca4 |
| publicationDate |
2010-12-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2010144848-A2 |
| titleOfInvention |
Stress balance layer on semiconductor wafer backside |
| abstract |
A semiconductor component (such as a semiconductor wafer or semiconductor die) includes a substrate having a front side and a back side. The semiconductor die/wafer also includes a stress balance layer on the back side of the substrate. An active layer deposited on the front side of the substrate creates an unbalanced stress in the semiconductor wafer/die. The stress balance layer balances stress in the semiconductor wafer/die. The stress in the stress balance layer approximately equals the stress in the active layer. Balancing stress in the semiconductor component prevents warpage of the semiconductor wafer/die. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2018133586-A |
| priorityDate |
2009-06-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |