| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a0f26a9c2efad3ae086a108f3c04b57d |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-26586
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-518
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-105 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-2652
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-26513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-2658
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1045
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7835
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823892
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0922
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1083 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate |
2010-03-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_75668926c6f15a03823bbb9b6df23701
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cd0168d3ca883d7f71da247ffd573152
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3f5417b477b92a2c171378ba5218565a |
| publicationDate |
2010-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2010110892-A1 |
| titleOfInvention |
Configuration and fabrication of semiconductor structure having extended-drain field-effect transistor |
| abstract |
An extended-drain insulated-gate field-effect transistor contains first and second source/drain zones laterally separated by a channel zone constituted by part of a first well region A gate dielectric layer overlies the channel zone A gate electrode overlies the gate dielectric layer above the channel zone The first source/drain zone is normally the source The second S/D zone, normally the drain, is at least partially constituted with a second well region A well-separating portion of the semiconductor body extends between the well regions and is more lightly doped than each well region The configuration of the well regions cause the maximum electric field in the IGFETs portion of the semiconductor body to occur well below the upper semiconductor surface, typically at or close to where the well regions are closest to each other The IGFET's operating characteristics are stable with operational time. |
| priorityDate |
2009-03-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |