| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_063a1b324005ddc15e16e7529c6258c4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d187ca60e550caca7b169a7428710597 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-15013
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-135
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K23-425 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K23-42
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K23-54
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-15 |
| filingDate |
2009-07-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d55dd5185d4e6e806e3336736df49eda |
| publicationDate |
2010-01-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2010004747-A1 |
| titleOfInvention |
Multi-phase clock divider circuit |
| abstract |
Provided is a divider circuit for a multi-phase clock signal which can assure a sufficient data latch time even for a multi-phase clock signal having a high frequency. For example, the divider circuit includes: a main latch circuit (10) which generates an inverse data signal by using two clock signals out of the 8-phase clock signals; and a sub latch circuit (20) which acquires the inverse data signal as a common data signal by using the 8-phase clock signals as a trigger. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2018522472-A |
| priorityDate |
2008-07-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |